How Chips Get Made

A transistorTransistorAn electrical switch with no moving parts — the only component a chip is really made of. is a voltage-controlled switch: current between source and drain is gated by the field applied at the gate. Scale that structure down, pack more of them per unit area, and you get more computation per unit of silicon, energy and cost. That single scaling relationship — historically labelled Moore's Law — is what has driven the industry for sixty years, and its slowing is what drives most of what is strange about the industry today.

Chips are printed, not assembled. The circuit pattern is projected photographically onto a silicon waferWaferThe mirror-polished disc of silicon that chips are printed onto — 300 mm across at the leading edge. — a mirror-polished disc, 300 mm across at the leading edge — coated in a light-sensitive photoresistPhotoresistThe light-sensitive coating on a wafer that records the projected pattern.. Light passing through a patterned maskPhotomask (reticle)The patterned plate the circuit design is projected through, at 4× final size. hardens the resist selectively; the unexposed material is chemically stripped; the exposed pattern is etched into the layer beneath; and a new film is deposited on top. Repeat that loop 60 to 100 times and you have built a three-dimensional structure of transistors and copper interconnect layer by layer. Around 1,000 individual process steps and roughly three months separate a blank wafer from a finished one.

One wafer carries hundreds of copies of the same chip, called diesDieOne individual chip, as cut from the wafer.. They are cut apart at the end, and the fraction that work is the yieldYieldThe fraction of chips on a wafer that actually work. — the number that decides whether a process node is a business or a science project. Yield is why a new node takes years to become profitable, and it is the single most useful number to ask about when a company claims to have caught up on process technology.

Process node names are not measurements. "3 nm", "2 nm" and "18A" describe generations, not dimensions; the correlation with physical feature size broke down around the 22 nm generation. What actually improves is transistor density, switching speed and energy per operation — and vendors define those differently, which is why TSMC N3, Samsung SF3 and Intel 3 are not equivalent despite the matching digit. Compare density and power figures, never names.

The industry is vertically disintegrated: the six stages of production sit in largely separate firms, and a company's position in that chain tells you more about it than its revenue does. The dominant structure is the fablessFablessA company that designs chips and owns no factories. / foundryFoundryA factory that manufactures other companies' chip designs on contract. split, pioneered when TSMC was founded in 1987 on the then-radical proposition of a factory that would build anyone's design and compete with none of them.

Design is architecture, RTL, verification and physical implementation — the fabless company's job (Nvidia, Qualcomm, Apple silicon, AMD, Broadcom). IPIP coreA pre-designed, pre-verified circuit block licensed rather than designed from scratch. and EDAEDAElectronic design automation — the software without which a modern chip cannot be designed at all. are the upstream inputs: Arm licenses instruction-set architectures and core designs; Synopsys and Cadence sell the software without which a modern chip cannot physically be designed, plus much of the interface IP. Tape-outTape-outThe moment a finished design is handed to the fab and frozen. is the handoff — the finished layout goes to the fab, photomasksPhotomask (reticle)The patterned plate the circuit design is projected through, at 4× final size. are made, and the design is frozen at a cost of tens to hundreds of millions of dollars per mask set at the leading edge.

Fabrication is the foundry's job, and it is where the capital lives: a leading-edge fab runs $20–30 billion. PackagingPackagingCutting the wafer into chips and mounting them in something solderable to a board. — once a low-margin afterthought done in Southeast Asia — has become a genuine bottleneck, because performance gains now come as much from how dies are connected as from what is on them. Test uses dedicated ATE hardware (Advantest, Teradyne) both at wafer level and after packaging. Then the chip ships to an OEM or ODM for board assembly.

Two structural facts follow. First, the leading edge is a capital filter: the number of companies able to fund a new node has fallen from more than twenty in 2001 to three today — TSMC, Samsung and Intel. Second, advanced packaging is now the acute constraint: as of 2026, TSMC's CoWoSCoWoSTSMC's advanced packaging: multiple dies mounted side by side on a silicon interposer. capacity is fully booked, with roughly one million wafers of demand, Nvidia holding an estimated 60% and the top three customers over 85%. When the press says AI chips are supply-constrained, packaging is usually what they mean — not wafer starts.

Read any company in this industry along two axes: which stage of the chain it occupies, and how substitutable it is at that stage. High revenue and low substitutability are different things, and conflating them is the most common error in mainstream coverage.

Chokepoints — no viable second source. ASML holds a complete monopoly on EUVEUVExtreme-ultraviolet lithography at 13.5 nm — made by ASML and nobody else. lithography and effectively owns the leading edge of DUVDUVDeep-ultraviolet lithography at 193 nm — the workhorse that prints most layers of most chips. immersion too. Synopsys and Cadence together hold roughly 74% of EDA (38% and 36%; about 85% including Siemens EDA), and no leading-edge design is possible without their toolchains. TSMC held roughly 72–73% of the pure-foundry market in Q1 2026 and a far higher share of genuinely leading-edge capacity. Arm supplies the instruction-set architecture beneath essentially every phone; RISC-V is a credible long-term alternative but not a drop-in one.

Strong but substitutable. Applied Materials, Lam Research and Tokyo Electron dominate deposition and etch, and KLA dominates process control — each is a leader with real competitors in adjacent segments, in a wafer-fab-equipment market worth about $92B in 2026. Nvidia leads AI accelerators overwhelmingly, but the moat is CUDA and system design rather than manufacturing; AMD, and increasingly Broadcom-built custom silicon, compete directly. Samsung and SK Hynix and Micron compete in memory as a genuine three-way oligopoly. GlobalFoundries exited the leading-edge race in 2018 and now runs a profitable specialty and mature-node business.

Constrained by controls. Huawei/HiSilicon designs competitive silicon it cannot have manufactured at the leading edge abroad, and SMIC manufactures for it at 7 nm-class using DUVDUVDeep-ultraviolet lithography at 193 nm — the workhorse that prints most layers of most chips. multipatterningMultipatterningPrinting one circuit layer in several passes, because a single exposure cannot resolve it. at yields reported around 20–40%. Both are the subject of §5.

Computing silicon lives on a specialisation spectrum, and the governing trade-off is generality against efficiency per operation. CPUs optimise single-thread latency: deep pipelines, aggressive out-of-order execution, large caches, sophisticated branch prediction — most of the die area spent on predicting and scheduling rather than arithmetic. GPUs optimise throughput: thousands of simple cores under a SIMT model, wide memory interfaces, and latency hidden by oversubscription rather than avoided. The workload has to be data-parallel to benefit, and dense linear algebra is.

ASICsASICA chip built to do exactly one job, extremely well, and nothing else. hard-wire a specific function, buying one to two orders of magnitude in performance per watt over a general-purpose part at the cost of NRE in the hundreds of millions and zero flexibility after tape-out. Google's TPU is the canonical AI example; Broadcom's custom-accelerator business exists to build these for hyperscalers. NPUsNPUA chip specialised for running neural networks efficiently, usually at low power. are ASICs specialised for neural-network inference — systolic MAC arrays, on-chip weight storage, aggressive quantisation support — and now appear in essentially every phone and laptop SoC. FPGAsFPGAA chip whose internal wiring can be reconfigured after it is manufactured. offer post-manufacture reconfigurability through a fabric of lookup tables and programmable interconnect; they win where volumes are too low to justify an ASIC or where the standard is still moving. AMD (Xilinx) holds roughly 51% of that market, Altera about 29%, Lattice about 7%.

Memory is a different industry with different economics — commodity-cyclical rather than design-differentiated, three suppliers, and violent price cycles. DRAMDRAMMain working memory — fast, and forgets everything the instant power is lost. stores each bit as charge on a capacitor that leaks and must be refreshed thousands of times a second; it is volatile and fast. NANDNAND flashStorage that keeps its contents without power — what SSDs are made of. traps charge in a floating gate and retains it without power, and modern parts stack 200-plus layers vertically. SRAMSRAMFast volatile memory built from six transistors per bit — what on-die caches are made of. — six transistors per bit, fast, volatile, expensive, and notably no longer scaling well with node shrinks — is what on-die caches are built from, and its stalled scaling is a genuine problem for future chip design.

HBMHBMHigh-bandwidth memory — DRAM stacked vertically and placed right beside the processor. deserves separate attention because it has become the AI bottleneck alongside packaging. It is DRAM dies stacked vertically, connected by through-silicon vias, and co-packaged with the processor on an interposer. HBM4 doubles the interface to 2,048 bits per stack, reaching 1.5–2 TB/s per stack against 896–1,280 GB/s for HBM3E, with capacity up to 64 GB per stack. Accelerator performance is now frequently memory-bandwidth-bound rather than FLOPs-bound, which is why HBM supply and pricing move the whole AI hardware market.

Lithography sets the floor on feature size, and EUVEUVExtreme-ultraviolet lithography at 13.5 nm — made by ASML and nobody else. at 13.5 nm is the current tool. ASML is the sole supplier, and the monopoly is one of systems integration rather than a single patent: the plasma light source (Cymer), the optics (Zeiss SMT, in a relationship that functionally excludes other customers), the high-power CO₂ drive laser (Trumpf), the vacuum architecture, and the stages and metrology that hold nanometre-scale overlay while wafers move at high acceleration.

Source physics. Roughly 50,000 tin droplets per second are injected into a vacuum vessel. Each is struck by a pre-pulse that flattens it into a pancake and then a main CO₂ pulse that ionises it into a plasma emitting at 13.5 nm. Because EUV is absorbed by all known refractive materials, the optical path is entirely reflective — multilayer Bragg mirrors of alternating molybdenum and silicon, each reflecting only about 70%, so a dozen reflections in series deliver a small fraction of the generated light to the wafer. Conversion efficiency and source power have been the binding constraints on throughput for a decade. Current NXE:3800E systems reach about 220 wafers per hour, a 37% improvement over the NXE:3600D.

High-NA. The EXE:5200 generation raises numerical aperture from 0.33 to 0.55, improving resolution at the cost of a halved field size — meaning large dies must be stitched from two exposures — and anamorphic optics that demagnify differently in each axis. Cost is roughly €380M (about $400M). As of September 2026, about 10 High-NA systems were reported live at four customers with three more shipping; Intel was first and has used High-NA in volume production for 18A Panther Lake, while TSMC is still evaluating R&D units. ASML expects roughly 65 Low-NA EUV shipments in 2026, with EUV making up 57% of net system sales in Q2 2026.

The rest of the toolchain is also concentrated. Deposition and etch are dominated by Applied Materials, Lam Research and Tokyo Electron; process control and metrology by KLA; coat/develop track by TEL and SCREEN; test by Advantest and Teradyne. Total wafer-fab equipment is roughly $92B in 2026. There is no complete non-Western toolchain, and this collective concentration — not lithography alone — is what makes export controls effective.

Each participant holds a different piece of an indivisible chain, and the resulting leverage map is the substance of semiconductor policy. United States: EDA (Synopsys, Cadence), a large share of chip design, much of the equipment base (AMAT, Lam, KLA), and extraterritorial reach through the Foreign Direct Product Rule, which asserts jurisdiction over foreign-manufactured items produced with US technology. Netherlands: ASML. Japan: TEL, Advantest, Nikon and Canon, plus a commanding position in photoresists, specialty chemicals and silicon wafers. Taiwan: more than 90% of leading-edge manufacturing. South Korea: memory, and HBM in particular. China: demand, mature-node capacity at scale, rare-earth and gallium/germanium processing — and no leading-edge lithography.

The control regime, in outline. October 2022 introduced performance thresholds on AI accelerators and restricted equipment sales for advanced logic, DRAM and NAND, plus a US-persons restriction on servicing Chinese advanced fabs. October 2023 closed the workaround chips designed to sit under the original thresholds. December 2024 extended controls to HBM and added a large tranche of entity listings. Through 2025–2026 the regime shifted toward licensed sales of specific parts rather than blanket bans: roughly ten Chinese firms including Alibaba, Tencent and ByteDance were cleared to buy Nvidia H200s with a 75,000-unit-per-customer cap, while Blackwell and Rubin top-end parts remain barred. Nvidia has reported that approved China volumes had generated no revenue, with import permission on the Chinese side unresolved. In mid-2026 Commerce clarified that licensing requirements follow corporate headquarters, extending to overseas subsidiaries of Chinese-parented firms.

Allied alignment is real but partial. Dutch rules since 2023 require licences for DUV immersion exports, extended in September 2024 to the 1970i and 1980i, and — significantly — to servicing, spare parts and software updates for previously sold restricted systems, since a scanner without support degrades within months. Japan imposed parallel restrictions. Friction persists: in April 2026 US Commerce questioned ASML over a possible EUV diversion to China, and US legislators proposed the MATCH Act to force tighter multilateral alignment.

What the controls actually block, and what they do not. They block EUV outright, restrict leading-edge DUV and the associated etch, deposition and metrology tools, restrict advanced AI accelerators, restrict HBM, and restrict servicing. They do not block mature-node production, where China is expanding aggressively, nor domestic Chinese design, nor — completely — smuggling and offshore compute access, both of which are active enforcement problems.